R01UH0823EJ0100 Rev.1.00 Page 369 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
18.3.6 DMAC Execution Cycles
Table 18.7 lists execution cycles in one DMAC data transfer operation.
Note 1. This is the case when the block size is 2 or more. When the block size is 1, normal transfer cycle is applied.
P: Block size (DMCRAH register setting)
Cr: Data read destination access cycle
Cw: Data write destination access cycle
Cr and Cw depend on the access destination. For the number of cycles for each access destination, see section 49, RAM,
section 50, Flash Memory (FLASH), and section 5, I/O Registers.
The unit for +1 in “Data Transfer (Read)” column is one system clock cycle (ICLK).
For the operation example, see
section 18.3.5, Operation Timing.
Table 18.7 DMAC Execution Cycles
Transfer Mode Data Transfer (Read) Data Transfer (Write)
Normal Cr+1 Cw
Repeat Cr+1 Cw
Block*
1
P × Cr P × Cw
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