R01UH0823EJ0100 Rev.1.00 Page 1264 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
36.3.2 Channel Modes
Figure 36.3 shows a channel mode state transition chart. Table 36.6 shows the channel mode transition time.
Figure 36.3 Channel Mode State Transition Chart
Table 36.6 Channel Mode Transition Time
Mode before Transition Mode after Transition Maximum Transition Time
Channel stop Channel reset 3 PCLK cycles
Channel reset Channel stop 3 PCLK cycles
Channel reset Channel halt 3 CAN bit times
Channel reset Channel communication 2 CAN bit times
Channel halt Channel reset 3 PCLK cycles
Channel halt Channel communication 3 CAN bit times
Channel communication Channel reset 3 PCLK cycles
Channel communication Channel halt 2 CAN frames
Channel communication mode
Channel stop mode
CAN reset
CSLPR = 0 CSLPR = 1
Channel reset mode
CHMDC[1:0] = 00b CHMDC[1:0] = 01b
Channel halt mode
CHMDC[1:0] = 00b
CHMDC[1:0] = 10b
*2
CHMDC[1:0] = 10b
CHMDC[1:0] = 01b
Reception
BOSTS = 0
TRMSTS = 0
RECSTS = 1
COMSTS = 1
Transmission
BOSTS = 0
TRMSTS = 1
RECSTS = 0
COMSTS = 1
Idle
BOSTS = 0
TRMSTS = 0
RECSTS = 0
COMSTS = 1
Bus off
BOSTS = 1
TRMSTS = 1
RECSTS = 0
COMSTS =1
SOF
detected
Reception
completed
Arbitration lost
11 consecutive
recessive bits have been
detected 128 times
(BOM[1:0] bits are set
to 00b) and transmission
start
TEC > 255
11 consecutive recessive bits
have been detected 128 times
(BOM[1:0] bits are set to 00b)
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CHMDC[1:0], CSLPR: Bits in the CTRL register
BOM[1:0]: Bits in the CTRH register
BOSTS, TRMSTS, RECSTS, COMSTS: Bits in the STSL register
Note 1. Timing of transition from bus off state to channel halt mode
• When BOM[1:0] = 01b: Transition to channel halt mode when TEC exceeds 255
• When BOM[1:0] = 10b: Transition to channel halt mode when 11 consecutive recessive bits have been detected 128 times
• When BOM[1:0] = 11b: Transition to channel halt mode when the CHMDC[1:0] bits are set to 10b
Note 2. While the CAN bus is locked at the dominant level, transition to channel halt mode is not made. In that case, enter channel reset mode.