Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1265 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
(1) Channel Stop Mode
In channel stop mode, clocks are not supplied to channels and therefore power consumption is reduced. CAN registers
can be read, but writing data to them is prohibited. Register values are retained.
Each channel enters channel stop mode after the operation of the CAN module is enabled. The channel transitions to
channel stop mode when the CTRL.CSLPR bit is set to 1 (channel stop mode) in channel reset mode.
The CSLPR bit should not be modified in channel communication mode and channel halt mode.
(2) Channel Reset Mode
In channel reset mode, channel settings are performed. When a channel transitions to channel reset mode, some channel-
related registers are initialized.
Table 36.8 lists the registers to be initialized.
When the CTRL.CHMDC[1:0] bits are set to 01b (channel reset mode) during CAN communication,
communication is terminated before it is completed and the channel transitions to channel reset mode.
Table 36.7 shows
the operation when the CTRL.CHMDC[1:0] bits are set to 01b (channel reset mode) during CAN communication.
(3) Channel Halt Mode
In channel halt mode, settings for test-related registers of channels are performed. When a channel transitions to channel
halt mode, CAN communication of the channel stops.
Table 36.7 shows operation when the CTRL.CHMDC[1:0] bits are set to 10b (channel halt mode) during CAN
communication.
Note 1. To allow transition to channel reset mode after communication is completed, set the CHMDC[1:0] bits to 10b and confirm that
communication has been completed and transition to channel halt mode has been made, and then set the CHMDC[1:0] bits to
01b.
Note 2. While the CAN bus is locked at the dominant level, transition to channel halt mode is not made. In that case, enter channel reset
mode. The CAN bus status can be confirmed with the ERFLL.BLF flag that becomes 1 when dominant lock is detected.
Note 3. In case of a transition from channel reset mode to channel halt mode, transition to channel halt mode after setting the CFGL and
CFGH registers in channel reset mode.
(4) Channel Communication Mode
In channel communication mode, CAN communication is performed. Each channel has the following communication
states during CAN communication.
 Idle: Neither reception nor transmission is in progress.
 Reception: Receiving a message sent from another node.
 Transmission: Transmitting a message.
Table 36.7 Operation when a Channel Transitions to Channel Reset Mode/Channel Halt Mode
Mode During Reception During Transmission Bus Off State
Channel reset
(CHMDC[1:0] = 01b)
Transitions to channel reset
mode before reception is
completed.*
1
Transitions to channel reset
mode before transmission is
completed.*
1
Transitions to channel reset mode before
bus off recovery.
Channel halt*
3
(CHMDC[1:0] = 10b)
Transitions to channel halt
mode after reception is
completed.*
2
Transitions to channel halt
mode after transmission is
completed.*
2
[When BOM[1:0] = 00b]
Transitions to channel halt mode
(CHMDC[1:0] = 10b) only after bus off
recovery.
[When BOM[1:0] = 01b]
Transitions to channel halt mode
automatically when the condition for
transition to bus off state is met.
[When BOM[1:0] = 10b]
Transitions to channel halt mode
automatically after bus off recovery.
[When BOM[1:0] = 11b]
Transitions to channel halt mode
immediately after the CHMDC[1:0] bits are
set to 10b before bus off recovery.

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English