R01UH0823EJ0100 Rev.1.00 Page 325 of 1823
Jul 31, 2019
RX23W Group 17. Memory-Protection Unit (MPU)
17.2.5 Memory-Protection Error Status-Clearing Register (MPECLR)
CLR B
it (
Error Status-Clearing
)
This bit clears the data read/write bit (DRW), the data memory-protection error generation bit (DMPER), and the
instruction memory-protection error generation bit (IMPER) in the memory-protection error status register (MPESTS) to
0.
Address(es): 0008 6508h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
————————————————
Value after reset:
0000000000000000
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
———————————————CLR
Value after reset:
0000000000000000
Bit Symbol Bit Name Function R/W
b0 CLR Error Status-Clearing [Reading]
0: Fixed value for reading
[Writing]
0: Nothing is done.
1: The DMPER and IMPER bits in MPESTS are cleared to 0.
R/W
b31 to b1 — Reserved The read value is 0. The write value should always be 0. R/W
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