R01UH0823EJ0100 Rev.1.00 Page 95 of 1823
Jul 31, 2019
RX23W Group 2. CPU
2.8.2 Numbers of Cycles for Response to Interrupts
Table 2.21 lists numbers of cycles taken by processing for response to interrupts.
Times calculated from the values in
Table 2.21 will be applicable when access to memory from the CPU is processed
with no waiting. The RAM and code flash memory in this MCU allow such access. Numbers of cycles for response to
interrupts can be minimized by placing program code (and vectors) in code flash memory and the stack in RAM.
Furthermore, place the addresses where the exception handling routine start on 8-byte boundaries.
For information on the number of cycles from notification to acceptance of the interrupt request, indicated by N in the
table above, see
Table 2.13 to Table 2.20.
The timing of interrupt acceptance depends on the execution state of the instruction. For more information on this, see
section 14.3.1, Acceptance Timing and Saved PC Value.
Table 2.21 Numbers of Cycles for Response to Interrupts
Type of Interrupt Request/Details of Processing Fast Interrupt Other Interrupts
ICU
Judgment of priority order
2 cycles
CPU
Number of cycles from notification to acceptance of
the interrupt request
N cycles
(varies with the instruction being executed at the time the interrupt was
received)
CPU Pre-processing by hardware
Saving the current PC and PSW values in RAM
(or in control registers in the case of the fast interrupt)
Reading of the vector
Branching to the start of the exception handling
routine
4 cycles 6 cycles
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