R01UH0823EJ0100 Rev.1.00 Page 694 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
25.3.4 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter.
This function works by counting the TPU1 (TPU4) count clock at overflow/underflow of TPU2.TCNT (TPU5.TCNT) as
set by the TPSC[2:0] bits in TPU1.TCR (TPSC[2:0] bits in TPU4.TCR).
Underflow occurs only when the lower 16-bit TPUm.TCNT is in phase counting mode.
Table 25.21 lists the register combinations used in cascaded operation.
Note: When phase counting mode is set for TPU1 or TPU4, the count clock setting is invalid and the counter operates
independently in phase counting mode.
(1) Example of Cascaded Operation Setting Procedure
Figure 25.17 shows an example of the setting procedure for cascaded operation.
Figure 25.17 Cascaded Operation Setting Procedure
Table 25.21 Cascaded Combinations
Combination Upper 16 Bits Lower 16 Bits
TPU1 and TPU2 TPU1.TCNT TPU2.TCNT
TPU4 and TPU5 TPU4.TCNT TPU5.TCNT
Set cascading
Cascaded operation
<Cascaded operation>
[1]
[2]
Start counting
[1] Set the TPSC[2:0] bits in TCR of TPU1 (TPU4) to
111b to select TPU2.TCNT (TPU5.TCNT)
overflow/underflow counting.
[2] Set the TPU.TSTR.CSTj bit (j = 0 to 5) for the
upper and lower channels to 1 to start count
operation.
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