Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 695 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
(2) Examples of Cascaded Operation
Figure 25.18 shows the operation when counting upon TPU2.TCNT overflow/underflow has been set for TPU1.TCNT,
TPU1.TGRB and TPU2.TGRB have been set as input capture registers, and the rising edge of the TIOCB1 and TIOCB2
pins has been selected.
When a rising edge is input to the TIOCB1 and TIOCB2 pins simultaneously, the upper 16 bits of the 32-bit data are
transferred to TPU1.TGRB, and the lower 16 bits to TPU2.TGRB. Note that a point for caution applies to simultaneous
input capture in cascade operation, as described in
section 25.9.11, TCNT Simultaneous Input Capture in Cascade
Operation
.
Figure 25.18 Example of Cascaded Operation (1)
Figure 25.19 shows the operation when counting upon TPU2.TCNT overflow/underflow has been set for TPU1.TCNT,
and phase counting mode 1 has been specified for TPU2.
TPU1.TCNT is incremented by TPU2.TCNT overflow and decremented by TPU2.TCNT underflow.
Figure 25.19 Example of Cascaded Operation (2)
TPU2.TCNT clock
TPU2.TCNT FFFFh 0000h 0001h
TPU1.TGRB
03A2h
TPU2.TGRB 0000h
TPU1.TCNT clock
TPU1.TCNT 03A1h 03A2h
TIOCB1, TIOCB2
TCLKC
TPU2.TCNT FFFDh
TPU1.TCNT
0001h
TCLKD
FFFEh FFFFh 0000h 0001h 0002h 0001h 0000h FFFFh
0000h 0000h

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)