R01UH0823EJ0100 Rev.1.00 Page 779 of 1823
Jul 31, 2019
RX23W Group 28. Realtime Clock (RTCe)
28.2.16 Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable
Register (BCNT3AER)
(1) In calendar count mode:
When the ENB bit in the RYRAREN register is set to 1, the RYRAR value is compared with the RYRCNT value. From
among the alarm registers (RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only
those selected with the ENB bits set to 1 are compared with the corresponding counters. When the respective values all
match, the IR flag corresponding to the ALM interrupt is set to 1.
This register is set to 00h by an RTC software reset.
(2) In binary count mode:
The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary
counter b31 to b24. Among the ENB[31:0] bits, the binary counter (BCNT[31:0]) corresponding to the bits which are set
to 1 and the binary alarm register (BCNTAR[31:0]) are compared, and when all match, the IR flag corresponding to the
ALM interrupt becomes 1.
This register is set to 00h by an RTC software reset.
Address(es): RTC.RYRAREN 0008 C41Eh
b7 b6 b5 b4 b3 b2 b1 b0
ENB———————
Value after reset:
xxxxxxxx
x: Undefined
Bit Symbol Bit Name Description R/W
b6 to b0 — Reserved Set these bits to 0. They are read as the set value. R/W
b7 ENB ENB 0: The register value is not compared with the RYRCNT counter value.
1: The register value is compared with the RYRCNT counter value.
R/W
Address(es): RTC.BCNT3AER 0008 C41Eh
b7 b6 b5 b4 b3 b2 b1 b0
ENB[31:24]
Value after reset:
xxxxxxxx
x: Undefined
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