R01UH0823EJ0100 Rev.1.00 Page 351 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
18.2.9 DMA Transfer Enable Register (DMCNT)
DTE Bit (DMA Transfer Enable)
When the DMST bit in DMAST is set to 1 (DMAC activation is enabled) and this bit is set to 1 (DMA transfer is
enabled), DMA transfer can be started for the corresponding channel.
[Setting condition]
When 1 is written to this bit.
[Clearing conditions]
When 0 is written to this bit.
When the specified total volume of data transfer is completed.
When DMA transfer is stopped by the repeat size end interrupt.
When DMA transfer is stopped by the extended repeat area overflow interrupt.
Address(es): DMAC0.DMCNT 0008 201Ch, DMAC1.DMCNT 0008 205Ch, DMAC2.DMCNT 0008 209Ch, DMAC3.DMCNT 0008 20DCh
b7 b6 b5 b4 b3 b2 b1 b0
———————DTE
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 DTE DMA Transfer Enable 0: Disables DMA transfer.
1: Enables DMA transfer.
R/W
b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W
To Next Page
Loading...
Need help?
General
