Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 966 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.2 Block Diagram of SCIg (SCI5)
Bus interface
External clock
SCKn
PCLK
PCLK/4
PCLK/16
PCLK/64
RTSn#/
CTSn#/
SSn#
RXDn/
SSCLn/
SMISOn
TXDn/
SSDAn/
SMOSIn
Internal peripheral bus
Clock
Module data bus
RDRH
RDR(L)
TDRH
TDR(L)
Transmission
and reception
control
SCMR
Baud rate
generator
BRR
MDDR
SSR
SCR
SMR
SEMR
SPMR
Parity addition
Parity check
TEI interrupt request
TXI interrupt request
RXI interrupt request
ERI interrupt request
SIMR1
SNFR
SIMR2
SIMR3
SISR
RSR TSR
RDR: Receive data register
RDRH: Receive data register H
RDRL: Receive data register L
RSR: Receive shift register
TDR: Transmit data register
TDRH: Transmit data register H
TDRL: Transmit data register L
TSR: Transmit shift register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
SCMR: Smart card mode register
BRR: Bit rate register
MDDR: Modulation duty register
SEMR: Serial extended mode register
SNFR: Noise filter setting register
SIMR1: I
2
C mode register 1
SIMR2: I
2
C mode register 2
SIMR3: I
2
C mode register 3
SISR: I
2
C status register
SPMR: SPI mode register
Error
Receive data full
Transmit data empty
Transmit end
Event output
TMO0
TMR
TMO1

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English