Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 1368 of 1823
Jul 31, 2019
RX23W Group 38. Serial Peripheral Interface (RSPIa)
(2) MSB First Transfer (24-Bit Data)
Figure 38.15 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity
disabled, 24 bits as the RSPI data length for an example that is not 32 bits, and MSB first selected.
In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are copied to the shift
register. Data for transmission are shifted out from the shift register in order from T23, through T22, and so on to T00.
In reception, received data are shifted in bit by bit through bit 0 of the shift register. When bits R23 to R00 have been
collected after input of the required number of cycles of RSPCK, the value in the shift register is copied to the receive
buffer. At this time, the higher-order 8 bits of the transmit buffer are stored in the higher-order 8 bits of the receive buffer.
Writing 0 to bits T31 to T24 at the time of transmission leads to 0 being inserted in the higher-order 8 bits of the receive
buffer.
Figure 38.15 MSB First Transfer (24-Bit Data, Parity Disabled)
Output
Transfer start
Transfer end
T31 T30 T29 T28 T27 T26 T25 T24 T23 T06 T05 T04 T03 T02 T01 T00
T31T30T29T28T27T26T25T24T23
T31 T30 T29 T28 T27 T26 T25 T24 R23
T31 T30 T29 T28 T27 T26 T25 T24 R23
T06 T05 T04 T03 T02 T01 T00
R06 R05 R04 R03 R02 R01
R00
R06 R05
T08 T07
T08 T07
R08 R07
R08 R07 R04 R03 R02 R01 R00
Shift register
Copy
Shift register
Input
Copy
Bit 0
Receive buffer
Bit 31
Bit 24 Bit 23
Bit 0Bit 31
Bit 24 Bit 23
Bit 0Bit 31
Bit 23
Transmit buffer
Bit 0Bit 31
Bit 23
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)