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R01UH0823EJ0100 Rev.1.00 Page 1336 of 1823

Jul 31, 2019

RX23W Group 38. Serial Peripheral Interface (RSPIa)

MODFEN Bit (Mode Fault Error Detection Enable)

The MODFEN bit enables or disables the detection of mode fault error (refer to

section 38.3.8, Error Detection). In

addition, the RSPI determines the I/O direction of the SSLA0, SSLA1, and SSLA3 pins based on combinations of the

MODFEN and MSTR bits (refer to

section 38.3.2, Controlling RSPI Pins).

MSTR Bit (RSPI Master/Slave Mode Select)

The MSTR bit selects master/slave mode of the RSPI. According to MSTR bit settings, the RSPI determines the

direction of pins RSPCKA, MOSIA, MISOA, SSLA0, SSLA1, and SSLA3.

SPEIE Bit (RSPI Error Interrupt Enable)

The SPEIE bit enables or disables the generation of RSPI error interrupt requests when the RSPI detects a mode fault

error and sets the SPSR.MODF flag to 1, when the RSPI detects an overrun error and sets the SPSR.OVRF flag to 1, or

when the RSPI detects a parity error and sets the SPSR.PERF flag to 1 (refer to

section 38.3.8, Error Detection).

SPTIE Bit (Transmit Buffer Empty Interrupt Enable)

The SPTIE bit enables or disables the generation of transmit buffer empty interrupt requests when the RSPI detects when

the transmit buffer is empty.

A transmit buffer empty interrupt request when transmission starts is generated by setting the SPE and SPTIE bits to 1 at

the same time or by setting the SPE bit to 1 after setting the SPTIE bit to 1.

Note that a transmit buffer interrupt is generated when the SPTIE bit is 1 even if the RSPI function is disabled (the SPTIE

bit is changed to 0).

SPE Bit (RSPI Function Enable)

The SPE bit enables or disables the RSPI function.

When the SPSR.MODF flag is 1, the SPE bit cannot be set to 1. For details, refer to

section 38.3.8, Error Detection.

Setting the SPE bit to 0 disables the RSPI function, and initializes a part of the module function. For details, refer to

section 38.3.9, Initializing RSPI. Furthermore, a transmit buffer empty interrupt request is generated by the state of the

SPE bit changing from 0 to 1 or from 1 to 0.

SPRIE Bit (RSPI Receive Buffer Full Interrupt Enable)

If the RSPI has detected a receive buffer full write after completion of a serial transfer, the SPRIE bit enables or disables

the generation of an RSPI receive buffer full interrupt request.

Renesas RX Series User Manual

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