Renesas RX Series

18.3.5 Operation Timing ..................................................................................................................... 368
18.3.6 DMAC Execution Cycles ......................................................................................................... 369
18.3.7 Activating the DMAC .............................................................................................................. 370
18.3.8 Starting DMA Transfer ............................................................................................................. 371
18.3.9 Registers during DMA Transfer ............................................................................................... 371
18.3.10 Channel Priority ........................................................................................................................ 372
18.4 Ending DMA Transfer ....................................................................................................................... 373
18.4.1 Transfer End by Completion of Specified Total Number of Transfer Operations ................... 373
18.4.2 Transfer End by Repeat Size End Interrupt .............................................................................. 373
18.4.3 Transfer End by Interrupt on Extended Repeat Area Overflow ............................................... 374
18.5 Interrupts ............................................................................................................................................ 375
18.6 Event Link Function .......................................................................................................................... 376
18.7 Low Power Consumption Function ................................................................................................... 377
18.8 Usage Notes ....................................................................................................................................... 378
18.8.1 DMA Transfer to Peripheral Modules ...................................................................................... 378
18.8.2 Access to the Registers during DMA Transfer ......................................................................... 378
18.8.3 DMA Transfer to Reserved Areas ............................................................................................ 378
18.8.4 Interrupt Request by the DMA Activation Source Flag Control Register (DMCSL)
at the End of each Transfer ....................................................................................................... 378
18.8.5 Setting of DMAC Activation Source Select Register of the Interrupt Controller
(ICU.DMRSRm) ....................................................................................................................... 378
18.8.6 Suspending or Restarting DMA Activation .............................................................................. 378
19. Data Transfer Controller (DTCa) .................................................................................................. 379
19.1 Overview ........................................................................................................................................... 379
19.2 Register Descriptions ......................................................................................................................... 381
19.2.1 DTC Mode Register A (MRA) ................................................................................................. 381
19.2.2 DTC Mode Register B (MRB) ................................................................................................. 382
19.2.3 DTC Transfer Source Register (SAR) ...................................................................................... 383
19.2.4 DTC Transfer Destination Register (DAR) .............................................................................. 383
19.2.5 DTC Transfer Count Register A (CRA) ................................................................................... 384
19.2.6 DTC Transfer Count Register B (CRB) ................................................................................... 385
19.
2.7 DTC Control Register (DTCCR) .............................................................................................. 385
19.2.8 DTC Vector Base Register (DTCVBR) ................................................................................... 386
19.2.9 DTC Address Mode Register (DTCADMOD) ......................................................................... 386
19.2.10 DTC Module Start Register (DTCST) ...................................................................................... 387
19.2.11 DTC Status Register (DTCSTS) ............................................................................................... 388
19.3 Request Sources ................................................................................................................................. 389
19.3.1 Allocating Transfer Information and DTC Vector Table ......................................................... 389
19.4 Operation ........................................................................................................................................... 391
19.4.1 Transfer Information Read Skip Function ................................................................................ 393
19.4.2 Transfer Information Write-Back Skip Function ..................................................................... 394
19.4.3 Normal Transfer Mode ............................................................................................................. 395