ADSP-21368 SHARC Processor Hardware Reference 4-27
Digital Audio/Digital Peripheral Interfaces
Figure 4-21. SRU_DAT3 Register
Figure 4-22. SRU_DAT4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Sample Rate Converter 3 TDM
Output Input
SRC3_TDM_OP_I
SRC1_TDM_OP_I
SRC2_TDM_OP_I
SRC0_TDM_OP_I
SRU_DAT3 (0x2443)
Reset = 0x00000000
SRC3_DAT_IP_I
Sample Rate Converter 2
TDM Output Input
Sample Rate Converter 1 TDM
Output Input
Sample Rate Converter 0 TDM
Output Input
Sample Rate Converter 3
Data Input Input
SRC1_TDM_OP_I
Sample Rate Converter 1
TDM Output Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
SPDIF Transmit
Data Input
DIT_DAT_I
IDP2_DAT_I
Input Data Port 2
Data Input
IDP3_DAT_I
Input Data Port 3 Data Input
IDP0_DAT_I
Input Data Port 0 Data Input
SRU_DAT4 (0x2444)
IDP1_DAT_I
Reset = 0x00000000
Input Data Port 1 Data Input
IDP1_DAT_I
Input Data Port 1
Data Input