Design Advantages
1-2 ADSP-21368 SHARC Processor Hardware Reference
and input/output (I/O) buses. In the core, every instruction can execute in
a single cycle. The buses and instruction cache provide rapid, unimpeded
data flow to the core to maintain the execution rate.
Figure 1-1 shows a detailed block diagram of the processor core and the
I/O processor (IOP). This figures illustrates the following architectural
features:
• Two processing elements (PEx and PEy), each containing 32-bit,
IEEE, floating-point computation units—multiplier, arithmetic
logic unit (ALU), shifter, and data register file
• Program sequencer with related instruction cache, interval timer,
and data address generators (DAG1 and DAG2)
• An SDRAM controller that provides an interface up to four sepa-
rate banks of industry-standard SDRAM devices or DIMMs, at
speeds up to
f
SCLK
• Up to 2M bits of SRAM and 6M bits of on-chip, mask-program-
mable ROM
• IOP with integrated direct memory access (DMA) controller, serial
peripheral interface (SPI) compatible port, and serial ports
(SPORTs) for point-to-point multiprocessor communications
• A variety of audio centric peripheral modules including a
Sony/Philips Digital Interface (S/PDIF), sample rate converter
(SRC) and pulse width modulation (PWM). Table 1-1 on page 1-5
provides details on these and other features for the current mem-
bers of the ADSP-21367/8/9 and ADSP-2137x processors families.
• JTAG test access port for emulation
Figure 1-1 also shows the three on-chip buses: the PM bus, DM bus, and
I/O bus. The PM bus provides access to either instructions or data. Dur-
ing a single cycle, these buses let the processor access two data operands
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