ADSP-21368 SHARC Processor Hardware Reference 13-17
Precision Clock Generators
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The combined PCGs can provide a selection of synchronous clock
frequencies to support alternate sample rates for the SRCs and
external DACs. However, the range of choices is limited by CLKIN
and the ratio of PCG_CLKx_O:SCLK:FSYNC which is normally fixed at
256:64:1 to support digital audio, left-justified, I
2
S, and right-jus-
tified interface modes. Many DACs also support 384, 512, and
786 × FSYNC for PCG_CLKx_O, which allows some additional flexibil-
ity in choosing CLKIN.
Note also that in all three DAI modes, the falling edge of SCLK
must always be synchronous with both edges of FSYNC. This
requires that the phase of the SCLK and FSYNC for a common PCG
be adjustable.
While the frequency of PCG_CLKx_O must be synchronous with the
sample rate supplied to the external DAC, there is no fixed-phase
requirement. For complete timing information, see the processor
specific data sheet.
Figure 13-6 shows an example of the internal interconnections between
the SPDIF receiver, SRC, and the PCGs. The interconnections are made
by programming the signal routing unit. Note that in this example, CCLK is
set at 242 MHz. This frequency can be adjusted up to the maximum CCLK
for the chosen processor. Also note that master clock (MCLK) is the input
source provided for the PCG. This input can come from CLKIN, any
peripheral output, or from one of the DAI pins.
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