Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 1004 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
IICRSTAREQ Bit (Restart Condition Generation)
When a restart condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b as well as setting
the IICRSTAREQ bit to 1.
[Setting condition]
 Writing 1 to the bit
[Clearing condition]
 Completion of generation of the restart condition
IICSTPREQ Bit (Stop Condition Generation)
When a stop condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b as well as setting the
IICSTPREQ bit to 1.
[Setting condition]
 Writing 1 to the bit
[Clearing condition]
 Completion of generation of the stop condition
IICSTIF Flag (Issuing of Start, Restart, or Stop Condition Completed Flag)
After generating a condition, this bit indicates that the generation is completed. When using the IICSTAREQ,
IICRSTAREQ, or IICSTPREQ bit to cause generation of a condition, do so after setting the IICSTIF flag to 0.
When the IICSTIF flag is 1 while an interrupt request is enabled by setting the SCR.TEIE bit, an STI request is output.
[Setting condition]
 Completion of the generation of a start, restart, or stop condition (however, in cases where this conflicts with any of
the conditions for the flag becoming 0 listed below, the other condition takes precedence)
[Clearing conditions]
 Writing 0 to the bit (confirm that the IICSTIF flag is 0 before doing so)
 Writing 0 to the SIMR1.IICM bit (when operation is not in simple I
2
C mode)
 Writing 0 to the SCR.TE bit
IICSDAS[1:0] Bits (SSDA Output Select)
These bits control output from the SSDAn pin.
Set the IICSDAS[1:0] and IICSCLS[1:0] bits to the same value during normal operations.
IICSCLS[1:0] Bits (SSCL Output Select)
These bits control output from the SSCLn pin.
Set the IICSCLS[1:0] and IICSDAS[1:0] bits to the same value during normal operations.