Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1083 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.66 Sample Flowchart for Reception of a Start Frame (2)
STR.BFDF = 1?
No
Yes
Set 1 to STCR.BFDCL
Set 1 to TCR.TCST
Set 1 to CR3.SDST
STR.CF0MF = 1?
No
Set 1 to STCR.CF0MCL
STR.PIBDF = 1?
No
Yes
Yes
Set 1 to STCR.PIBDCL
STR.CF1MF = 1?
Set 1 to STCR.CF1MCL
No
Yes
B
Information Frame communications
Start the timer counter so that determining the
Break Field is possible.
Begin detection of the Start Frame.
The STR.BFDF flag is set to 1 on detection of the
Break Field low width. At this time, if the ICR.BFDIE
bit is 1, an SCIX0 interrupt is generated.
Clear the STR.BFDF flag.
If the data received in Control Field 0 matches the
comparison data, the STR.CF0MF flag is set. An
SCIX1 interrupt is also generated if the value of the
ICR.CF0MIE bit is 1.
Clear the STR.CF0MF flag.
If there is a match with the priority interrupt bit in
Control Field 1, the STR.PIBDF flag becomes 1. An
SCIX1 interrupt is also generated if the value of the
ICR.PIBDIE bit is 1.
If there is a match with the data received in Control
Field 1, the STR.CF1MF flag is set. An SCIX1
interrupt is also generated if the value of the
ICR.CF1MIE bit is 1.
Clear the CF1MF and PIBDF flags in the STR
register.
Send the Information Frame.

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English