Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1160 of 1823
Jul 31, 2019
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.19 Slave Receive Operation Timing (1) (7-Bit Address Format, when RDRFS bit is 0)
Figure 35.20 Slave Receive Operation Timing (2) (when RDRFS bit is 0)
7-bit address + W
Read ICDRR register
(Dummy read
[7-bit address + W])
Automatic low hold
(to prevent failure to receive data)
7-bit slave address
X (ACK/NACK)
XXXX (Initial value/last data for reception)
0(ACK)
9
TDRE
MST
TRS
BBSY
TEND
S
NACKF
START
ICDRT
ICDRS
DATA 2
W
2
b6
3
b5
4
b4
5
b3
6
b2
7
b1
2
b6
4
b4
5
b3
6
b2
7
b1
3
b5
8
b0
1
b7
2
b6
4
b4
3
b5
DATA 1 DATA 2
RDRF
ICDRR
ACKBT
ACKBR
[3]
1
b7
DATA 1
[3][4]
8
b0
9 1
b7
DATA 1
AASy
Receive data (7-bit address + W)
Receive data (DATA 1)
XXXX (Initial value/last data for transmission)
7-bit address + W
0 (ACK)
0(ACK)
Read ICDRR
register
(DATA 1)
ACKACK
SCL0
SDA0
XXXX (Initial value/last data for transmission)
0 (ACK)
Read ICDRR
register
(DATA n-2)
TDRE
MST
TRS
BBSY
TEND
STOP
ICDRT
ICDRS
DATA n
2
b6
4
b4
5
b3
6
b2
7
b1
3
b5
8
b0
1
b7
2
b6
4
b4
5
b3
6
b2
7
b1
3
b5
8
b0
8
b0
1
b7
7
b1
DATA n-1 DATA nDATA n-2
RDRF
ICDRR
99
ACKBT
ACKBR
[3] [4]
NACKF
AASy
9 P
[3] [4] [3] [4] [6]
Receive data (DATA n)Receive data (DATA n-1)
DATA n-2 DATA n-1
DATA n-1DATA n-3 DATA n-2
0(ACK)
0(ACK)
Read ICDRR
register
(DATA n-1)
Read ICDRR
register
(DATA n)
Clear
STOP flag
Receive data (DATA n-2)
ACK
ACK ACK
0(ACK)
DATA n
SCL0
SDA0

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English