Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1168 of 1823
Jul 31, 2019
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.28 AASy/DID Flag Set/Clear Timing during Reception of Device-ID
[When address before the device-ID + R does not match the slave address]
[When address received after a restart condition is detected does not match the device-ID ]
Device-ID match (1111 100b + W)
S 9Sr23456711
to
8 9834567981
2
[Device-ID reception]
The previous value is retained.
Slave address match
Receive data (7-bit address/lower 10 bits)
R
ACK
TDRE
AASy
TRS
BBSY
RDRF
ACK
Address
1
DID
Slave address match
AASy
BBSY
ACK
Address
DID
R/W
Slave address mismatch
Device-ID mismatch
RDRF
W
W
001 1 1 1
001 1 1 1
001 1 1 1
7-bit slave address (other station)
AASy
BBSY
DID
TDRE
001 1 1 1 R NACK NACK 1 001 1 1 1 R NACK
Comparing the second and the following
bytes is stopped.
RDRF
ACK ACK
ACK1
1
1
Read ICDRR register
(Dummy read [7-bit address/lower 10 bits])
S 9Sr23456711
to
8 9834567981
2
Receive data (7-bit address/lower 10 bits)
Device-ID match (1111 100b + W)
Read ICDRR register
(Dummy read [7-bit address/lower 10 bits])
S 9Sr23456711
to
8 9834567981
2
Device-ID match (1111 100b + R) Device-ID match (1111 100b + R)
Device-ID match (1111 100b + R)
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)