Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 1232 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
This bit is set to 0 when the following conditions are met.
 Receive mode: Global reset mode
 Transmit mode: Channel reset mode
Modify this bit only in the following mode.
 Receive mode: Global operating mode or global test mode
 Transmit mode: Channel communication mode or channel halt mode
CFRXIE Bit (Transmit/Receive FIFO Receive Interrupt Enable)
When the CFSTS0.CFRXIF flag becomes 1 while this bit is 1, a transmit/receive FIFO receive interrupt request is
generated.
Modify this bit with the CFE bit set to 0.
CFTXIE Bit (Transmit/Receive FIFO Transmit Interrupt Enable)
When the CFSTS0.CFTXIF flag becomes 1 while this bit is 1, a transmit/receive FIFO transmit interrupt request is
generated.
Modify this bit with the CFE bit set to 0 (no transmit/receive FIFO buffer is used).
CFDC[2:0] Bits (Transmit/Receive FIFO Buffer Depth Configuration)
These bits are used to set the number of messages that can be stored in a single transmit/receive FIFO buffer.
If these bits are set to 000b, do not use any receive FIFO buffer. Modify these bits only in global reset mode.
CFIM Bit (Transmit/Receive FIFO Interrupt Source Select)
This bit is used to select a transmit/receive FIFO interrupt source. Modify this bit only in global reset mode.
CFIGCV[2:0] Bits (Transmit/Receive FIFO Receive Interrupt Request Timing Select)
These bits are used to specify the fraction of the transmit/receive FIFO buffer (the number of messages is selected by the
setting of the CFDC[2:0] bits) that must be filled for the FIFO buffer to generate a receive interrupt request when the
CFCCH0.CFM[1:0] bits are set to 00b (receive mode) and the CFIM bit is set to 0.
When the CFDC[2:0] bits are set to 001b (4 messages), set the CFIGCV[2:0] bits to 001b, 011b, 101b, or 111b.
Modify these bits only in global reset mode.