R01UH0823EJ0100 Rev.1.00 Page 1290 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
Figure 36.25 FIFO Buffer Reception Timing Chart
(1) When the ID field in a message has been received, the acceptance filter processing starts.
(2) When the message matches the receive rule of the corresponding channel and the message has been successfully
received, the routing processing to transfer the message to the specified buffer starts. When the GCFGL.DCE bit is
set to 1 (DLC check is enabled), the DLC filter processing starts at this time.
(3) When the message has passed through the DLC filter processing and the CFCCL0.CFE value is 1 (transmit/receive
FIFO buffers are used) and the CFCCL0.CFDC[2:0] value is 001b or more, the message is stored in the transmit/
receive FIFO buffer that is set to receive mode. The CFSTS0.CFMC[5:0] value is incremented and becomes 01h.
When the CFCCL0.CFIM bit is set to 1 (a FIFO receive interrupt request is generated each time a message has been
received), the CFSTS0.CFRXIF flag becomes 1 (a transmit/receive FIFO receive interrupt request is present). The
CFSTS0.CFRXIF flag can be reset to 0 by the program.
(4) When the ID field of the next message has been received, the acceptance filter processing starts.
(5) Read received messages from the CFIDL0, CFIDH0, CFTS0, CFPTR0, and CFDF00 to CFDF30 registers and write
FFh to the CFPCTR0 register. Thereby the CFSTS0.CFMC[5:0] flags are decremented and become 00h, and the
CFSTS0.CFEMP flag becomes 1 (the transmit/receive FIFO buffer contains no message (buffer empty)).
(6) When the message matches the receive rule of the corresponding channel and the message has been successfully
received, the routing processing to transfer the message to the specified buffer starts. When the GCFGL.DCE bit is
set to 1 (DLC check is enabled), the DLC filter processing starts at this time.
(7) The message is stored in the transmit/receive FIFO buffer set in receive mode, when the message has passed
through the DLC filter process if the CFCCL0.CFE bit is set to 1 (transmit/receive FIFO buffers are used) and the
CFDC[2:0], CFE: Bits in the CFCCL0 register
CFMC[5:0], CFEMP, CFRXIF: Bits in the CFSTS0 register
RFDC[2:0], RFE: Bits in the RFCCm register
RFMC[5:0], RFEMP, RFIF: Flags in the RFSTSm register
SOF
Acceptance
filter processing
EOF
INT
CRC
delimiter
High
Low
CAN bus
1
CFDC[2:0] bits
ID
Control
ID
Control
EOF
INT
ACK SOF ACK
(1) (2) (3) (4) (5) (6) (7)
Acceptance
filter processing
Routing and storage
processing
Routing and storage
processing
0101
0
[Transmit/receive FIFO buffer (receive mode)]
CFE bit
1
0
CFMC[5:0] flags
CFEMP flag
1
0
CFRXIF flag
1
0
3
RFDC[2:0] bits
0 1
0
[Receive FIFO buffer]
RFE bit
1
0
RFMC[5:0] flags
RFEMP flag
1
0
RFIF flag
1
0
Cleared by the program
To Next Page
Loading...
Need help?
General
