Renesas RX Series

20.4.2 Setting Bit-Rotating Operation of Output Port Groups ............................................................ 429
20.4.3 Linking DMA/DTC Transfer End Signal as Event .................................................................. 429
20.4.4 Clock Settings ........................................................................................................................... 429
20.4.5 Module Stop Function Setting .................................................................................................. 429
21. I/O Ports ....................................................................................................................................... 430
21.1 Overview ........................................................................................................................................... 430
21.2 I/O Port Configuration ....................................................................................................................... 432
21.3 Register Descriptions ......................................................................................................................... 441
21.3.1 Port Direction Register (PDR) .................................................................................................. 441
21.3.2 Port Output Data Register (PODR) .......................................................................................... 442
21.3.3 Port Input Data Register (PIDR) .............................................................................................. 443
21.3.4 Port Mode Register (PMR) ....................................................................................................... 444
21.3.5 Open Drain Control Register 0 (ODR0) ................................................................................... 445
21.3.6 Open Drain Control Register 1 (ODR1) ................................................................................... 446
21.3.7 Pull-Up Control Register (PCR) ............................................................................................... 447
21.3.8 Drive Capacity Control Register (DSCR) ................................................................................ 448
21.4 Initialization of the Port Direction Register (PDR) ........................................................................... 449
21.5 Handling of Unused Pins ................................................................................................................... 450
22. Multi-Function Pin Controller (MPC) ............................................................................................ 451
22.1 Overview ........................................................................................................................................... 451
22.2 Register Descriptions ......................................................................................................................... 457
22.2.1 Write-Protect Register (PWPR) ................................................................................................ 457
22.2.2 P0n Pin Function Control Register (P0nPFS) (n = 3, 5, 7) ...................................................... 458
22.2.3 P1n Pin Function Control Registers (P1nPFS) (n = 4 to 7) ...................................................... 459
22.2.4 P2n Pin Function Control Register (P2nPFS) (n = 1, 2, 5 to 7) ............................................... 460
22.2.5 P3n Pin Function Control Registers (P3nPFS) (n = 0, 1) ......................................................... 461
22.2.6 P4n Pin Function Control Registers (P4nPFS) (n = 0 to 7) ...................................................... 462
22.2.7 PBn Pin Function Control Registers (PBnPFS) (n = 0, 1, 3, 5, 7) ........................................... 463
22.2.8 PCn Pin Function Control Registers (PCnPFS) (n = 0, 2 to 7) ................................................ 464
22.2.9 PDn Pin Function Control Registers (PDnPFS) (n = 3) ........................................................... 465
22
.2.10 PEn Pin Function Control Registers (PEnPFS) (n = 0 to 4) ..................................................... 466
22.2.11 PJn Pin Function Control Registers (PJnPFS) (n = 3) .............................................................. 468
22.3 Usage Notes ....................................................................................................................................... 469
22.3.1 Procedure for Specifying Input/Output Pin Function ............................................................... 469
22.3.2 Notes on MPC Register Setting ................................................................................................ 469
22.3.3 Note on Using Analog Functions ............................................................................................. 470
22.3.4 Notes on Using the CTSU Function of the Capacitive Touch Sensing Unit ............................ 470
23. Multi-Function Timer Pulse Unit 2 (MTU2a) ................................................................................. 471
23.1 Overview ........................................................................................................................................... 471
23.2 Register Descriptions ......................................................................................................................... 476
23.2.1 Timer Control Register (TCR) ................................................................................................. 476