26.2.3 Time Constant Register B (TCORB) ........................................................................................ 732
26.2.4 Timer Control Register (TCR) ................................................................................................. 733
26.2.5 Timer Counter Control Register (TCCR) ................................................................................. 734
26.2.6 Timer Control/Status Register (TCSR) .................................................................................... 736
26.2.7 Timer Counter Start Register (TCSTR) .................................................................................... 738
26.3 Operation ........................................................................................................................................... 739
26.3.1 Pulse Output ............................................................................................................................. 739
26.3.2 External Counter Reset Input ................................................................................................... 740
26.4 Operation Timing .............................................................................................................................. 741
26.4.1 TCNT Count Timing ................................................................................................................ 741
26.4.2 Timing of Interrupt Signal Output on a Compare Match ......................................................... 742
26.4.3 Timing of Timer Output Signal at Compare Match ................................................................. 742
26.4.4 Timing of Counter Clear by Compare Match ........................................................................... 743
26.4.5 Timing of the External Reset for TCNT ................................................................................... 743
26.4.6 Timing of Interrupt Signal Output on an Overflow .................................................................. 744
26.5 Operation with Cascaded Connection ............................................................................................... 745
26.5.1 16-Bit Count Mode ................................................................................................................... 745
26.5.2 Compare Match Count Mode ................................................................................................... 745
26.6 Interrupt Sources ................................................................................................................................ 746
26.6.1 Interrupt Sources and DTC Activation ..................................................................................... 746
26.7 Link Operation by ELC ..................................................................................................................... 747
26.7.1 Event Signal Output to ELC ..................................................................................................... 747
26.7.2 TMR Operation when Receiving an Event Signal from ELC .................................................. 747
26.7.3 Notes on Operating TMR According to an Event Signal from ELC ........................................ 748
26.8 Usage Notes ....................................................................................................................................... 749
26.8.1 Module Stop State Setting ........................................................................................................ 749
26.8.2 Notes on Setting Cycle ............................................................................................................. 749
26.8.3 Conflict between TCNT Write and Counter Clear ................................................................... 749
26.8.4 Conflict between TCNT Write and Increment ......................................................................... 750
26.8.5 Conflict between TCORA or TCORB Write and Compare Match .......................................... 750
26.8.6 Conflict between Compare Matches A and B .......................................................................... 751
26.8.7 Switching of Internal Clocks and TCNT Operation .........
........................................................ 751
26
.8.8 Clock Source Setting with Cascaded Connection .................................................................... 753
26.8.9 Continuous Output of Compare Match Interrupt Signal .......................................................... 753
27. Compare Match Timer (CMT) ...................................................................................................... 754
27.1 Overview ........................................................................................................................................... 754
27.2 Register Descriptions ......................................................................................................................... 755
27.2.1 Compare Match Timer Start Register 0 (CMSTR0) ................................................................ 755
27.2.2 Compare Match Timer Start Register 1 (CMSTR1) ................................................................ 755
27.2.3 Compare Match Timer Control Register (CMCR) ................................................................... 756
27.2.4 Compare Match Counter (CMCNT) ......................................................................................... 757
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