25.2.9 Timer Synchronous Register (TSYR) ...................................................................................... 680
25.2.10 Noise Filter Control Register (NFCR) ...................................................................................... 681
25.3 Operation ........................................................................................................................................... 683
25.3.1 Basic Functions ......................................................................................................................... 683
25.3.2 Synchronous Operation ............................................................................................................ 689
25.3.3 Buffer Operation ....................................................................................................................... 691
25.3.4 Cascaded Operation .................................................................................................................. 694
25.3.5 PWM Modes ............................................................................................................................. 696
25.3.6 Phase Counting Mode ............................................................................................................... 701
25.3.6.1 Phase Counting Mode Application Example .................................................................. 706
25.3.7 Noise Filters .............................................................................................................................. 707
25.4 Interrupt Sources ................................................................................................................................ 708
25.5 DTC Activation ................................................................................................................................. 709
25.6 DMAC Activation ............................................................................................................................. 709
25.7 A/D Converter Activation ................................................................................................................. 709
25.8 Operation Timing .............................................................................................................................. 710
25.8.1 Input/Output Timing ................................................................................................................. 710
25.8.2 Interrupt Signal Timing ............................................................................................................ 714
25.9 Usage Notes ....................................................................................................................................... 716
25.9.1 Module Stop Function Setting .................................................................................................. 716
25.9.2 Input Clock Restrictions ........................................................................................................... 716
25.9.3 Notes on Cycle Setting ............................................................................................................. 716
25.9.4 Conflict between TPUm.TCNT Write and Clear Operations ................................................... 717
25.9.5 Conflict between TPUm.TCNT Write and Increment Operations ........................................... 717
25.9.6 Conflict between TPUm.TGRy Write and Compare Match .................................................... 718
25.9.7 Conflict between Buffer Register Write and Compare Match ................................................. 718
25.9.8 Conflict between TPUm.TGRy Read and Input Capture ......................................................... 719
25.9.9 Conflict between TPUm.TGRy Write and Input Capture ........................................................ 719
25.9.10 Conflict between Buffer Register Write and Input Capture ..................................................... 720
25.9.11 TCNT Simultaneous Input Capture in Cascade Operation ...................................................... 720
25.9.12 Conflict between Overflow/Underflow and Counter Clearing ................................................. 721
25.9.13 Conflict between TPUm.TCNT Write and Overflow/Underflow ............................................ 722
25.9.14 Multiplexing of I/O Pins ........................................................................................................... 722
25.9.15 Continuous Output of Compare-Match Pulse Interrupt Signal ................................................ 723
25
.9.16 Continuous Output of Input-Capture Pulse Interrupt Signal .................................................... 724
25.9.17 Continuous Output of Underflow Pulse Interrupt Signal ......................................................... 725
26. 8-Bit Timer (TMR) ........................................................................................................................ 726
26.1 Overview ........................................................................................................................................... 726
26.2 Register Descriptions ......................................................................................................................... 731
26.2.1 Timer Counter (TCNT) ............................................................................................................ 731
26.2.2 Time Constant Register A (TCORA) ....................................................................................... 732
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