23.7.3 Overview of Pin Initialization Procedures and Mode Transitions
in Case of Error during Operation ............................................................................................ 612
23.8 Operations Linked by the ELC .......................................................................................................... 638
23.8.1 Event Signal Output to the ELC ............................................................................................... 638
23.8.2 MTU Operations in Response to Receiving Event Signals from the ELC ............................... 638
23.8.3 Notes on MTU by Event Signal Reception from the ELC ....................................................... 639
24. Port Output Enable 2 (POE2a) .................................................................................................... 640
24.1 Overview ........................................................................................................................................... 640
24.2 Register Descriptions ......................................................................................................................... 643
24.2.1 Input Level Control/Status Register 1 (ICSR1) ........................................................................ 643
24.2.2 Output Level Control/Status Register 1 (OCSR1) ................................................................... 645
24.2.3 Input Level Control/Status Register 2 (ICSR2) ........................................................................ 646
24.2.4 Software Port Output Enable Register (SPOER) ..................................................................... 647
24.2.5 Port Output Enable Control Register 1 (POECR1) .................................................................. 648
24.2.6 Port Output Enable Control Register 2 (POECR2) .................................................................. 649
24.2.7 Input Level Control/Status Register 3 (ICSR3) ........................................................................ 650
24.3 Operation ........................................................................................................................................... 651
24.3.1 Input Level Detection Operation .............................................................................................. 653
24.3.2 Output-Level Compare Operation ............................................................................................ 654
24.3.3 High-Impedance Control Using Registers ................................................................................ 655
24.3.4 High-Impedance Control on Detection of Stopped Oscillation ................................................ 655
24.3.5 High-Impedance Control in Response to Receiving an Event Signal from the ELC ............... 655
24.3.6 Release from the High-Impedance ........................................................................................... 655
24.4 Interrupts ............................................................................................................................................ 656
24.5 Usage Notes ....................................................................................................................................... 656
24.5.1 Transitions to Software Standby Mode .................................................................................... 656
24.5.2 When the POE Is Not Used ...................................................................................................... 656
24.5.3 Specifying Pins Corresponding to the MTU ............................................................................ 656
24.5.4 Notes on High-Impedance Control by Event Signal Reception from the ELC ........................ 656
25. 16-Bit Timer Pulse Unit (TPUa) ................................................................................................... 657
25.1 Overview ....................................................
....................................................................................... 657
25.2 Register Descriptions ......................................................................................................................... 661
25.2.1 Timer Control Register (TCR) ................................................................................................. 661
25.2.2 Timer Mode Register (TMDR) ................................................................................................. 665
25.2.3 Timer I/O Control Register (TIORH, TIORL, TIOR) .............................................................. 666
25.2.4 Timer Interrupt Enable Register (TIER) .................................................................................. 674
25.2.5 Timer Status Register (TSR) .................................................................................................... 675
25.2.6 Timer Counter (TCNT) ............................................................................................................ 678
25.2.7 Timer General Register A (TGRA), Timer General Register B (TGRB),
Timer General Register C (TGRC), Timer General Register D (TGRD) ................................ 678
25.2.8 Timer Start Register (TSTR) .................................................................................................... 679
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