R01UH0823EJ0100 Rev.1.00 Page 261 of 1823
Jul 31, 2019
RX23W Group 14. Exception Handling
When an exception is accepted, hardware processing by the RXv2 CPU is followed by access to the vector to acquire the
address of the branch destination. In the vector, a vector address is allocated to each exception, and the branch destination
address of the exception handling routine is written to each vector address.
Hardware pre-processing by the RXv2 CPU handles saving of the contents of the program counter (PC) and processor
status word (PSW). In the case of a fast interrupt, the contents are saved in the backup PC (BPC) and the backup PSW
(BPSW), respectively. In the case of exceptions other than a fast interrupt, the contents are saved in the stack area.
General purpose registers and control registers other than the PC and PSW that are to be used within the exception
handling routine must be saved on the stack by a user program at the start of the exception handling routine.
On completion of processing by an exception handling routine, registers saved on the stack are restored and the RTE
instruction is executed to restore execution from the exception handling routine to the original program. For return from
a fast interrupt, the RTFI instruction is used instead. In the case of a non-maskable interrupt, however, finish the program
or reset the system without returning to the original program.
Hardware post-processing by the RXv2 CPU handles restoration of the contents of PC and PSW. In the case of a fast
interrupt, the values of BPC and BPSW are restored to PC and PSW, respectively. In the case of exceptions other than a
fast interrupt, the values are restored from the stack to PC and PSW.
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