Renesas RX Series - Page 28

32.2.26 Pipe Window Select Register (PIPESEL) ................................................................................ 893
32.2.27 Pipe Configuration Register (PIPECFG) .................................................................................. 894
32.2.28 Pipe Maximum Packet Size Register (PIPEMAXP) ................................................................ 896
32.2.29 Pipe Cycle Control Register (PIPEPERI) ................................................................................. 897
32.2.30 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) .................................................................. 898
32.2.31 PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 1 to 5) ................................... 906
32.2.32 PIPEn Transaction Counter Register (PIPEnTRN) (n = 1 to 5) ............................................... 907
32.2.33 Device Address n Configuration Register (DEVADDn) (n = 0 to 5) ...................................... 908
32.2.34 USB Module Control Register (USBMC) ................................................................................ 909
32.2.35 BC Control Register 0 (USBBCCTRL0) ................................................................................. 910
32.3 Operation ........................................................................................................................................... 912
32.3.1 System Control ......................................................................................................................... 912
32.3.1.1 Setting Data to the USB Related Register ....................................................................... 912
32.3.1.2 Controller Function Selection .......................................................................................... 912
32.3.1.3 Controlling USB Data Bus Resistors .............................................................................. 912
32.3.1.4 Example of USB External Connection Circuit ................................................................ 913
32.3.2 Interrupt Sources ....................................................................................................................... 920
32.3.3 Interrupt Descriptions ............................................................................................................... 922
32.3.3.1 BRDY Interrupt ............................................................................................................... 922
32.3.3.2 NRDY Interrupt ............................................................................................................... 926
32.3.3.3 BEMP Interrupt ............................................................................................................... 929
32.3.3.4 Device State Transition Interrupt .................................................................................... 930
32.3.3.5 Control Transfer Stage Transition Interrupt .................................................................... 931
32.3.3.6 Frame Update Interrupt ................................................................................................... 932
32.3.3.7 VBUS Interrupt ............................................................................................................... 932
32.3.3.8 Resume Interrupt ............................................................................................................. 932
32.3.3.9 OVRCR Interrupt ............................................................................................................ 932
32.3.3.10 BCHG Interrupt ............................................................................................................... 932
32.3.3.11 DTCH Interrupt ............................................................................................................... 932
32.3.3.12 SACK Interrupt ............................................................................................................... 933
32.3.3.13 SIGN Interrupt ......................................................................................................
........... 933
32.3.3.
14 ATTCH Interrupt ............................................................................................................. 933
32.3.3.15 EOFERR Interrupt ........................................................................................................... 933
32.3.3.16 Portable Device Detection Interrupt ................................................................................ 933
32.3.4 Pipe Control .............................................................................................................................. 934
32.3.4.1 Pipe Control Register Switching Procedures .................................................................. 935
32.3.4.2 Transfer Types ................................................................................................................. 935
32.3.4.3 Endpoint Number ............................................................................................................ 935
32.3.4.4 Maximum Packet Size Setting ......................................................................................... 936
32.3.4.5 Transaction Counter (For PIPE1 to PIPE5 in Reading Direction) .................................. 936
32.3.4.6 Response PID .................................................................................................................. 937