32.3.4.7 Data PID Sequence Bit .................................................................................................... 938
32.3.4.8 Response PID = NAK Function ...................................................................................... 938
32.3.4.9 Auto Response Mode ...................................................................................................... 938
32.3.4.10 OUT-NAK Mode ............................................................................................................. 938
32.3.4.11 Null Auto Response Mode .............................................................................................. 939
32.3.5 FIFO Buffer Memory ............................................................................................................... 939
32.3.5.1 FIFO Buffer Memory ...................................................................................................... 939
32.3.5.2 FIFO Buffer Clearing ...................................................................................................... 940
32.3.5.3 FIFO Port Functions ........................................................................................................ 941
32.3.5.4 DMA Transfers (D0FIFO and D1FIFO Ports) ................................................................ 942
32.3.6 Control Transfers Using DCP ................................................................................................... 943
32.3.6.1 Control Transfers When the Host Controller is Selected ................................................ 943
32.3.6.2 Control Transfers When the Function Controller is Selected ......................................... 944
32.3.7 Bulk Transfers (PIPE1 to PIPE5) ............................................................................................. 945
32.3.8 Interrupt Transfers (PIPE6 to PIPE9) ....................................................................................... 945
32.3.8.1 Interval Counter during Interrupt Transfers When the Host Controller is Selected ........ 945
32.3.9 Isochronous Transfers (PIPE1 and PIPE2) ............................................................................... 946
32.3.9.1 Error Detection in Isochronous Transfers ....................................................................... 946
32.3.9.2 Data PID .......................................................................................................................... 947
32.3.9.3 Interval Counter ............................................................................................................... 947
32.3.10 SOF Interpolation Function ...................................................................................................... 954
32.3.11 Pipe Schedule ........................................................................................................................... 955
32.3.11.1 Conditions for Generating a Transaction ........................................................................ 955
32.3.11.2 Transfer Schedule ............................................................................................................ 955
32.3.11.3 Enabling USB Communication ....................................................................................... 955
32.4 Usage Notes ....................................................................................................................................... 956
32.4.1 Setting the Module Stop Function ............................................................................................ 956
32.5 Battery Charging Detection Processing ............................................................................................. 957
32.5.1 Processing When Function Controller is Selected ................................................................... 957
32.5.2 Processing When Host Controller is Selected .......................................................................... 959
33. Serial Communications Interface (SCIg, SCIh) ...............
............................................................. 962
33.1
Overview ........................................................................................................................................... 962
33.2 Register Descriptions ......................................................................................................................... 970
33.2.1 Receive Shift Register (RSR) ................................................................................................... 970
33.2.2 Receive Data Register (RDR) ................................................................................................... 970
33.2.3 Receive Data Register H, L, HL (RDRH, RDRL, RDRHL) .................................................... 971
33.2.4 Transmit Data Register (TDR) ................................................................................................. 971
33.2.5 Transmit Data Register H, L, HL (TDRH, TDRL, TDRHL) ................................................... 972
33.2.6 Transmit Shift Register (TSR) .................................................................................................. 972
33.2.7 Serial Mode Register (SMR) .................................................................................................... 973
33.2.8 Serial Control Register (SCR) .................................................................................................. 977
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