Renesas RX Series

35. I
2
C-bus Interface (RIICa) ............................................................................................................1113
35.1 Overview ......................................................................................................................................... 1113
35.2 Register Descriptions ....................................................................................................................... 1116
35.2.1 I
2
C-bus Control Register 1 (ICCR1) ...................................................................................... 1116
35.2.2 I
2
C-bus Control Register 2 (ICCR2) ...................................................................................... 1118
35.2.3 I
2
C-bus Mode Register 1 (ICMR1) ........................................................................................ 1122
35.2.4 I
2
C-bus Mode Register 2 (ICMR2) ........................................................................................ 1123
35.2.5 I
2
C-bus Mode Register 3 (ICMR3) ........................................................................................ 1125
35.2.6 I
2
C-bus Function Enable Register (ICFER) ........................................................................... 1127
35.2.7 I
2
C-bus Status Enable Register (ICSER) ............................................................................... 1129
35.2.8 I
2
C-bus Interrupt Enable Register (ICIER) ............................................................................ 1131
35.2.9 I
2
C-bus Status Register 1 (ICSR1) ......................................................................................... 1133
35.2.10 I
2
C-bus Status Register 2 (ICSR2) ......................................................................................... 1136
35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2) .................................................................. 1139
35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2) .................................................................. 1140
35.2.13 I
2
C-bus Bit Rate Low-Level Register (ICBRL) ..................................................................... 1141
35.2.14 I
2
C-bus Bit Rate High-Level Register (ICBRH) .................................................................... 1142
35.2.15 I
2
C-bus Transmit Data Register (ICDRT) .............................................................................. 1144
35.2.16 I
2
C-bus Receive Data Register (ICDRR) ............................................................................... 1144
35.2.17 I
2
C-bus Shift Register (ICDRS) ............................................................................................. 1144
35.3 Operation ......................................................................................................................................... 1145
35.3.1 Communication Data Format ................................................................................................. 1145
35.3.2 Initial Settings ......................................................................................................................... 1146
35.3.3 Master Transmit Operation ..................................................................................................... 1147
35.3.4 Master Receive Operation ...................................................................................................... 1150
35.3.5 Slave Transmit Operation ....................................................................................................... 1156
35.3.6 Slave Receive Operation ........................................................................................................ 1159
35.4 SCL Synchronization Circuit ........................................................................................................... 1161
35.5 SDA Output Delay Function ........................................................................................................... 1162
35.6 Digital Noise Filter Circuit .............................................................................................................. 1163
35.7 Address Match Detection ................................................................................................................ 1164
35.7.1 Slave-Address Match Detection ............................................................................................. 1164
35.7.2 Detection of the General Call Address ................................................................................... 1166
35.7.3 Device-ID Address Detection ................................................................................................. 1167
35.7.4 Host Address Detection .......................................................................................................... 1169
35.8 Automatic Low-Hold Function for SCL ......................................................................................... 1170
35.8.1 Function to Prevent Wrong Transmission of Transmit Data .................................................. 1170
35.8.2 NACK Reception Transfer Abort Function ............................................................................ 1171
35.8.3 Function to Prevent Failure to Receive Data .......................................................................... 1172
35.9 Arbitration-Lost Detection Functions .............................................................................................. 1174
35.9.1 Master Arbitration-Lost Detection (MALE Bit) .................................................................... 1174