R01UH0823EJ0100 Rev.1.00 Page 348 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
SARA[4:0] Bits (Source Address Extended Repeat Area)
These bits specify the extended repeat area on the source address. The extended repeat area function is realized by
updating the specified lower address bits with the remaining upper address bits fixed. The size of the extended repeat
area can be any power of two between 21 (2 bytes) and 217 (128 Mbytes).
When the lower address overflows the extended repeat area by address increment, the start address of the extended repeat
area is set. Similarly, when the lower address underflows the extended repeat area by address decrement, the end address
of the extended repeat area is set.
When the repeat area or block area is specified as a transfer source, do not specify the extended repeat area on the source
address. When repeat transfer or block transfer is selected, or when DMACm.DMTMD.DTS[1:0] = 01b (the transfer
source is specified as the repeat area or block area), write 00000b in the SARA[4:0] bits.
An interrupt can be requested when an overflow or underflow occurs in the extended repeat area with the SARIE bit in
DMINT set to 1.
Table 18.2 lists the settings and the corresponding extended repeat areas.
SM[1:0] Bit (Source Address Update Mode)
These bits select the mode of updating the source address.
When increment is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the source address is
incremented by 1, 2, and 4, respectively.
When decrement is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the source address is
decremented by 1, 2, and 4, respectively.
When offset addition is selected, the offset specified by the DMAC0.DMOFR register is added to the address.
Offset addition can be specified only for DMAC0.
To Next Page
Loading...
Need help?
General
