Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 489 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
x: Don't care
Note 1. When the MTU3.TMDR.BFA bit is set to 1 and the MTU3.TGRC register is used as a buffer register, this setting is invalid and
input capture/output compare is not generated.
x: Don't care
Table 23.23 TIORL (MTU3)
Bit 3 Bit 2 Bit 1 Bit 0 Description
IOC[3] IOC[2] IOC[1] IOC[0] MTU3.TGRC Function MTIOC3C Pin Function
0 0 0 0 Output compare register*
1
Output prohibited
0 0 0 1 Initial output is low.
Low output at compare match.
0 0 1 0 Initial output is low.
High output at compare match.
0 0 1 1 Initial output is low.
Toggle output at compare match.
0 1 0 0 Output prohibited
0 1 0 1 Initial output is high.
Low output at compare match.
0 1 1 0 Initial output is high.
High output at compare match.
0 1 1 1 Initial output is high.
Toggle output at compare match.
1 x 0 0 Input capture register*
1
Input capture at rising edge.
1 x 0 1 Input capture at falling edge.
1 x 1 x Input capture at both edges.
Table 23.24 TIORH (MTU4)
Bit 3 Bit 2 Bit 1 Bit 0 Description
IOA[3] IOA[2] IOA[1] IOA[0] MTU4.TGRA Function MTIOC4A Pin Function
0 0 0 0 Output compare register Output prohibited
0 0 0 1 Initial output is low.
Low output at compare match.
0 0 1 0 Initial output is low.
High output at compare match.
0 0 1 1 Initial output is low.
Toggle output at compare match.
0 1 0 0 Output prohibited
0 1 0 1 Initial output is high.
Low output at compare match.
0 1 1 0 Initial output is high.
High output at compare match.
0 1 1 1 Initial output is high.
Toggle output at compare match.
1 x 0 0 Input capture register Input capture at rising edge.
1 x 0 1 Input capture at falling edge.
1 x 1 x Input capture at both edges.