R01UH0823EJ0100 Rev.1.00 Page 682 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
NFDEN Bit (Noise Filter Enable D)
This bit disables or enables the noise filter for the TIOCDm pin (m = 3).
Since unexpected edges may be internally generated when the value of NFDEN is changed, select the output compare
function in the timer I/O control register before changing the NFDEN value.
NFCS[1:0] Bits (Noise Filter Clock Select)
These bits select the sampling clock for the noise filter.
When the count source is selected with NFCS[1:0] bits set to 11b, the clock that can be used as sampling clock are the
internal clocks other than PCLK/1 specified with the TPSC[2:0] bits and the external clock. To select the PCLK/1 as both
the count clock and the sampling clock, set the NFCS[1:0] bits to 00b.
The input-capture signal is sampled on rising edges of the selected clock signal. If the sampled levels match three times
in a row, the given level is passed through as the input-capture signal. If the levels do not match, the existing value is
retained.
After setting the NFCS[1:0] bits, wait for two selected sampling periods before setting the input capture function.
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