R01UH0823EJ0100 Rev.1.00 Page 684 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
(b) Free-running count operation and periodic count operation
Immediately after a reset, TPUm.TCNT are all set as free-running counters. When the relevant bit in TPU.TSTR is set to
1, the corresponding TCNT starts up-count operation as a free-running counter. When TCNT overflows (changes from
FFFFh to 0000h), the TPU requests an interrupt. After an overflow, TCNT restarts counting up from 0000h.
Figure 25.3 shows free-running counter operation.
Figure 25.3 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT for the relevant channel performs periodic
count operation. The TPUm.TGRy for setting the period is set as an output compare register, and counter clearing by
compare match is selected by the TPUm.TCR.CCLR[2:0] bits. After the settings have been made, TCNT starts count-up
operation as a periodic counter when the corresponding bit in TPU.TSTR is set to 1. When the count value matches the
TGRy value, TCNT is cleared to 0000h.
At this time, the TPU requests an interrupt. After a compare match, TCNT restarts counting up from 0000h.
Figure 25.4 shows periodic counter operation.
Figure 25.4 Periodic Counter Operation
TCNT value
FFFFh
0000h
TCImV interrupt
Time
TGImy interrupt
Counter cleared by TGRy compare match
TCNT value
C000h
0000h
Time
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