Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 77 of 1823
Jul 31, 2019
RX23W Group 2. CPU
Note 1. Writing 0 to the bit clears it. Writing 1 to the bit does not affect its value.
Note 2. Positive denormalized numbers are treated as +0, negative denormalized numbers as –0.
Note 3. When the EV bit is set to 0, the FV flag is enabled.
Note 4. When the EO bit is set to 0, the FO flag is enabled.
Note 5. When the EZ bit is set to 0, the FZ flag is enabled.
Note 6. When the EU bit is set to 0, the FU flag is enabled.
Note 7. When the EX bit is set to 0, the FX flag is enabled.
Note 8. Once the bit has been set to 1, this value is retained until it is cleared to 0 by software.
The floating-point status word (FPSW) indicates the results of floating-point operations.
When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified
by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the
occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has
been set to 1, this value is retained until it is cleared to 0 by software (j = X, U, Z, O, or V).
RM[1:0] Bits (Floating-Point Rounding-Mode Setting)
These bits specify the floating-point rounding-mode.
Explanation of Floating-Point Rounding Modes
(1) Rounding to the nearest value is specified as the default mode and returns the most accurate value.
(2) Modes such as rounding towards 0, rounding towards +
, and rounding towards – are used to ensure precision when
interval arithmetic is employed.
CV Flag (Invalid Operation Cause Flag), CO Flag (Overflow Cause Flag),
CZ Flag (Division-by-Zero Cause Flag), CU Flag (Underflow Cause Flag),
CX Flag (Inexact Cause Flag), and CE Flag (Unimplemented Processing Cause Flag)
Floating-point exceptions include the five specified in the IEEE754 standard, namely overflow, underflow, inexact,
division-by-zero, and invalid operation. For a further floating-point exception that is generated upon detection of
unimplemented processing, the corresponding flag (CE) is set to 1.
 The bit that has been set to 1 is cleared to 0 when the FPU instruction is executed.
 When 0 is written to the bit by the MVTC and POPC instructions, the bit is set to 0; the bit retains the previous value
when 1 is written by the instruction.
DN Flag (0 Flush Bit of Denormalized Number)
When this bit is set to 0, a denormalized number is handled as a denormalized number. When this bit is set to 1, a
denormalized number is handled as 0.
EV Bit (Invalid Operation Exception Enable), EO Bit (Overflow Exception Enable),
EZ Bit (Division-by-Zero Exception Enable), EU Bit (Underflow Exception Enable), and
EX Bit (Inexact Exception Enable)
When any of five floating-point exceptions specified in the IEEE754 standard is generated by the floating-point
b31 FS Floating-Point Error Summary Flag This bit reflects the logical OR of the FU, FZ, FO, and FV
flags.
R
 Rounding towards the nearest value
(the default behavior)
: An inexact result is rounded to the available value that is closest to the result which would be
obtained with an infinite number of digits. If two available values are equally close, rounding is
to the even alternative.
 Rounding towards 0 : An inexact result is rounded to the smallest available absolute value, i.e. in the direction of
zero (simple truncation).
 Rounding towards + : An inexact result is rounded to the nearest available value in the direction of positive infinity.
 Rounding towards – : An inexact result is rounded to the nearest available value in the direction of negative infinity.
Bit Symbol Bit Name Description R/W

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English