R01UH0823EJ0100 Rev.1.00 Page 809 of 1823
Jul 31, 2019
RX23W Group 29. Low-Power Timer (LPT)
LPCMRE0 Bit (Compare Match 0 Enable)
This bit enables or disables low-power timer compare match 0.
When the low-power timer is put into operation and the MCU makes a transition to software standby mode while this bit
and the LPWUCR.LPWKUPEN bit are set to 1 (wakeup from software standby mode using low-power timer is enabled),
the MCU returns from software standby mode to normal operating mode through the event link controller (ELC) when
the value of the low-power timer counter and the setting of the LPCMR0 register matches.
Modify this bit while the LPTCR3.LPCNTEN bit is 0 (low-power timer counter stops).
Do not write to this bit while the LPTCR3.LPCNTEN bit is 1 (low-power timer counter operates).
Settings for the interrupt and ELC are necessary to use a compare match 0 as a trigger source to return from software
standby mode.
Refer to
section 20, Event Link Controller (ELC) for details on the ELC settings, and refer to section 15, Interrupt
Controller (ICUb)
for details on the interrupt settings.
An interrupt request at compare match 0 is generated only in software standby mode. It is not generated in normal
operating mode, sleep mode, and deep sleep mode.
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