Renesas RX Series

6.3.8 Determination of Reset Generation Source .............................................................................. 147
7. Option-Setting Memory (OFSM) .................................................................................................. 148
7.1 Overview ........................................................................................................................................... 148
7.2 Register Descriptions ......................................................................................................................... 149
7.2.1 Option Function Select Register 0 (OFS0) ............................................................................... 149
7.2.2 Option Function Select Register 1 (OFS1) ............................................................................... 153
7.2.3 Endian Select Register (MDE) ................................................................................................. 154
7.3 Usage Note ........................................................................................................................................ 155
7.3.1 Setting Example of Option-Setting Memory ............................................................................ 155
8. Voltage Detection Circuit (LVDAb) ............................................................................................... 156
8.1 Overview ........................................................................................................................................... 156
8.2 Register Descriptions ......................................................................................................................... 158
8.2.1 Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1) ............................................... 158
8.2.2 Voltage Monitoring 1 Circuit Status Register (LVD1SR) ....................................................... 159
8.2.3 Voltage Monitoring Circuit Control Register (LVCMPCR) .................................................... 160
8.2.4 Voltage Detection Level Select Register (LVDLVLR) ........................................................... 161
8.2.5 Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0) ............................................... 162
8.3 VCC Input Voltage Monitor .............................................................................................................. 163
8.3.1 Monitoring Vdet0 ..................................................................................................................... 163
8.3.2 Monitoring Vdet1 ..................................................................................................................... 163
8.4 Reset from Voltage Monitor 0 ........................................................................................................... 164
8.5 Interrupt and Reset from Voltage Monitoring 1 ................................................................................ 165
8.6 Event Link Output ............................................................................................................................. 167
8.6.1 Interrupt Handling and Event Linking ...................................................................................... 167
9. Clock Generation Circuit .............................................................................................................. 168
9.1 Overview ........................................................................................................................................... 168
9.2 Register Descriptions ......................................................................................................................... 172
9.2.1 System Clock Control Register (SCKCR) ................................................................................ 172
9.2.2 System Clock Control Register 3 (SCKCR3) ........................................................................... 174
9.2.3 PLL Control Register (PLLCR) ............................................................................................... 175
9.2.4 PLL Control Register 2 (PLLCR2) .......................................................................................... 176
9.2.5 USB-dedicated PLL Control Register (UPLLCR) ................................................................... 177
9.2.6 USB-dedicated PLL Control Register 2 (UPLLCR2) .............................................................. 178
9.2.7 Main Clock Oscillator Control Register (MOSCCR) ............................................................... 179
9.2.8 Sub-Clock Oscillator Control Register (SOSCCR) .................................................................. 180
9.2.9
Low-Speed On-Chip Oscillator Control Register (LOCOCR) ................................................. 181
9.2.10 IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR) ...................................... 182
9.2.11 High-Speed On-Chip Oscillator Control Register (HOCOCR) ............................................... 183
9.2.12 High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) .......................................... 184
9.2.13 Oscillation Stabilization Flag Register (OSCOVFSR) ............................................................. 185
9.2.14 Oscillation Stop Detection Control Register (OSTDCR) ......................................................... 187