Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 964 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Note 1. In simple I
2
C mode, only MSB first is available.
Asynchronous
mode
Data length 7, 8, or 9 bits
Transmission stop bit 1 or 2 bits
Parity Even parity, odd parity, or no parity
Receive error detection Parity, overrun, and framing errors
Hardware flow control CTSn# and RTSn# pins can be used in controlling transmission/reception.
Start-bit detection Low level or falling edge is selectable.
Break detection When a framing error occurs, a break can be detected by reading the RXDn pin level
directly.
Clock source An internal or external clock can be selected.
Transfer rate clock input from the TMR can be used.
Double-speed mode Baud rate generator double-speed mode is selectable.
Multi-processor
communications function
Serial communication among multiple processors
Noise cancellation The signal paths from input on the RXDn pins incorporate digital noise filters.
Clock
synchronous
mode
Data length 8 bits
Receive error detection Overrun error
Hardware flow control CTSn# and RTSn# pins can be used in controlling transmission/reception.
Smart card
interface mode
Error processing An error signal can be automatically transmitted when detecting a parity error during
reception
Data can be automatically retransmitted when receiving an error signal during transmission
Data type Both direct convention and inverse convention are supported.
Simple I
2
C
mode
Transfer format I
2
C-bus format
Operating mode Master (single-master operation only)
Transfer rate Fast mode is supported (refer to section 33.2.11, Bit Rate Register (BRR) to set the
transfer rate).
Noise cancellation The signal paths from input on the SSCLn and SSDAn pins incorporate digital noise filters,
and the interval for noise cancellation is adjustable.
Simple SPI
bus
Data length 8 bits
Detection of errors Overrun error
SS input pin function Applying the high level to the SSn# pin can cause the output pins to enter the
high-impedance state.
Clock settings Four kinds of settings for clock phase and clock polarity are selectable.
Extended
serial mode
Start Frame transmission
 Output of a low level as the Break Field over a specified width and generation of
interrupts on completion
 Detection of bus collisions and the generation of interrupts on detection
Start Frame reception
 Detection of the Break Field low width and generation of an interrupt on detection
 Comparison of Control Fields 0 and 1 and generation of an interrupt when the two match
 Two kinds of data for comparison (primary and secondary) can be set in Control Field 1.
 A priority interrupt bit can be set in Control Field 1.
 Handling of Start Frames that do not include a Break Field
 Handling of Start Frames that do not include a Control Field 0
 Function for measuring bit rates
I/O control function
 Selectable polarity for TXDX12 and RXDX12 signals
 Selection of a digital filter for the RXDX12 signal
 Half-duplex operation employing RXDX12 and TXDX12 signals multiplexed on the same
pin
 Selectable timing for the sampling of data received through RXDX12
Timer function
 Usable as a reloading timer
Bit rate modulation function Correction of outputs from the on-chip baud rate generator can reduce errors.
Table 33.2 SCIh Specifications (2/2)
Item Description

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English