Texas Instruments CC3235 SimpleLink Series - DSLPWAKECFG Register

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.44 DSLPWAKECFG Register (offset = 108h) [reset = 0h]
DSLPWAKECFG is shown in Figure 15-47 and described in Table 15-47.
Figure 15-47. DSLPWAKECFG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EXITDSLPBYN
WPEN
EXITDSLPBYT
MREN
R-0h R/W-0h R/W-0h
Table 15-47. DSLPWAKECFG Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 EXITDSLPBYNWPEN R/W 0h
DSLP_WAKE_FROM_NWP_ENABLE
0h = Disable NWP to wake APPS from deep-sleep
1h = Enable the NWP to wake APPS from deep-sleep
0 EXITDSLPBYTMREN R/W 0h
DSLP_WAKE_TIMER_ENABLE
0h = Disable deep-sleep wake timer in APPS RCM
1h = Enable deep-sleep wake timer in APPS RCM for deep-sleep