Texas Instruments CC3235 SimpleLink Series - SHAMD5_IDIGEST_A Register; SHAMD5_IDIGEST_A Register Field Descriptions

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SWRU543–January 2019
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SHA/MD5 Accelerator
19.2.9 SHAMD5_IDIGEST_A Register (Offset = 20h) [reset = 0h]
SHAMD5_IDIGEST_A is shown in Figure 19-13 and described in Table 19-20.
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WRITE: Inner / Initial Digest [127:96] for MD5 [159:128] for SHA-1, [255:224] for SHA-2 / HMAC Key
[287:256] for HMAC key proc
READ: Intermediate / Inner Digest [127:96] for MD5 [159:128] for SHA-1, [255:224] for SHA-2 /
Result Digest/MAC [127:96] for MD5 [159:128] for SHA-1, [223:192] for SHA-2 224, [255:224] for SHA-2
256
Figure 19-13. SHAMD5_IDIGEST_A Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-20. SHAMD5_IDIGEST_A Register Field Descriptions
Bit Field Type Reset Description
31-0 DATA R/W 0h
Data