Texas Instruments CC3235 SimpleLink Series - MMCHS_ISE Register; MMCHS_ISE Register Field Descriptions

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SWRU543–January 2019
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SD Host Controller Interface
11.7.16 MMCHS_ISE Register (Offset = 238h) [reset = 0h]
Interrupt Signal Enable register
MMCHS_ISE is shown in Figure 11-17 and described in Table 11-20.
Return to Summary Table.
This register allows to enable or disable the module internal sources of status, on an event-by-event basis.
MMCHS_ISE[31:16] = Error Interrupt Signal Enable
MMCHS_ISE[15:0] = Normal Interrupt Signal Enable
Figure 11-17. MMCHS_ISE Register
31 30 29 28 27 26 25 24
RESERVED BADA_SIGEN CERR_SIGEN RESERVED
R-0h R/W-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED DEB_SIGEN DCRC_SIGEN DTO_SIGEN RESERVED CEB_SIGEN RESERVED CTO_SIGEN
R-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
NULL RESERVED
R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED BRR_SIGEN BWR_SIGEN RESERVED TC_SIGEN CC_SIGEN
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-20. MMCHS_ISE Register Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h
29 BADA_SIGEN R/W 0h
Bad access to data space signal status enable
0h = Masked
1h = Enabled
28 CERR_SIGEN R/W 0h
Card error interrupt signal status enable
0h = Masked
1h = Enabled
27-23 RESERVED R 0h
22 DEB_SIGEN R/W 0h
Data end bit error signal status enable
0h = Masked
1h = Enabled
21 DCRC_SIGEN R/W 0h
Data CRC error signal status enable
0h = Masked
1h = Enabled
20 DTO_SIGEN R/W 0h
Data time-out error signal status enable
0h = Masked
1h = Enabled
19 RESERVED R 0h
18 CEB_SIGEN R/W 0h
Command end bit error signal status enable
0h = Masked
1h = Enabled
17 RESERVED R 0h