Register Description
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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.4 DMA_ALTBASE Register (offset = Ch) [reset = C8h]
DMA_ALTBASE is shown in Figure 4-10 and described in Table 4-14.
This register returns the base address of the alternate channel control data. This register removes the
necessity for application software to calculate the base address of the alternate channel control
structures..
Figure 4-10. DMA_ALTBASE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R/W-C8h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-14. DMA_ALTBASE Register Field Descriptions
Bit Field Type Reset Description
31-0 ADDR R/W C8h Alternate Channel Address.
This field provides the base address of the alternate channel control
structures
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