ADC_MODULE Registers
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SWRU543–January 2019
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Analog-to-Digital Converter (ADC)
13.4 ADC_MODULE Registers
Table 13-2 lists the memory-mapped registers for the ADC_MODULE. All register offset addresses not
listed in Table 13-2 should be considered as reserved locations and the register contents should not be
modified. Base address for ADC_MODULE = 0x4402E800.
Table 13-2. ADC_MODULE Registers
Offset Acronym Register Name Section
0h ADC_CTRL ADC Control Section 13.4.1.1
24h ADC_CH0_IRQ_EN Channel 0 Interrupt Enable Section 13.4.1.2
2Ch ADC_CH2_IRQ_EN Channel 2 Interrupt Enable Section 13.4.1.3
34h ADC_CH4_IRQ_EN Channel 4 Interrupt Enable Section 13.4.1.4
3Ch ADC_CH6_IRQ_EN Channel 6 Interrupt Enable Section 13.4.1.5
44h ADC_CH0_IRQ_STATUS Channel 0 Interrupt Status Section 13.4.1.6
4Ch ADC_CH2_IRQ_STATUS Channel 2 Interrupt Status Section 13.4.1.7
54h ADC_CH4_IRQ_STATUS Channel 4 Interrupt Status Section 13.4.1.8
5Ch ADC_CH6_IRQ_STATUS Channel 6 Interrupt Status Section 13.4.1.9
64h ADC_DMA_MODE_EN DMA Mode Enable Section 13.4.1.10
68h ADC_TIMER_CONFIGURATION ADC Timer Configuration Section 13.4.1.11
70h ADC_TIMER_CURRENT_COUNT ADC Timer Current Count Section 13.4.1.12
74h CHANNEL0FIFODATA CH0 FIFO DATA Section 13.4.1.13
7Ch CHANNEL2FIFODATA CH2 FIFO DATA Section 13.4.1.14
84h CHANNEL4FIFODATA CH4 FIFO DATA Section 13.4.1.15
8Ch CHANNEL6FIFODATA CH6 FIFO DATA Section 13.4.1.16
94h ADC_CH0_FIFO_LVL Channel 0 Interrupt Status Section 13.4.1.17
9Ch ADC_CH2_FIFO_LVL Channel 2 Interrupt Status Section 13.4.1.18
A4h ADC_CH4_FIFO_LVL Channel 4 Interrupt Status Section 13.4.1.19
ACh ADC_CH6_FIFO_LVL Channel 6 Interrupt Status Section 13.4.1.20
B8h ADC_CH_ENABLE ADC Enable Register for Application Channels Section 13.4.1.21
13.4.1 ADC Register Description
The remainder of this section lists and describes the ADC registers, in numerical order by address offset.
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