Texas Instruments CC3235 SimpleLink Series - DMA_REQMASKSET Register; DMA_REQMASKSET Register Field Descriptions

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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.9 DMA_REQMASKSET Register (offset = 20h) [reset = 0h]
DMA_REQMASKSET is shown in Figure 4-15 and described in Table 4-19.
Each bit of this register represents the corresponding DMA channel. Setting a bit disables DMA requests
for the channel. Reading the register returns the request mask status. When a DMA channel's request is
masked, that means the peripheral can no longer request DMA transfers. The channel can then be used
for software-initiated transfers.
Figure 4-15. DMA_REQMASKSET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SET_n
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-19. DMA_REQMASKSET Register Field Descriptions
Bit Field Type Reset Description
31-0 SET_n R/W 0h Channel [n] Request Mask.
Set Bit 0 corresponds to channel 0.
A bit can only be cleared by setting the corresponding CLR[n] bit in
the DMAREQMASKCLR register.
0h = The peripheral associated with channel [n] is enabled to
request DMA transfers
1h = The peripheral associated with channel [n] is not able to
request DMA transfers. Channel [n] may be used for software-
initiated transfers.