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Flash Registers
775
SWRU543–January 2019
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On-Chip Parallel Flash
21.5.7 FMC2 Register (Offset = 20h) [reset = 0h]
FMC2 is shown in Figure 21-7 and described in Table 21-8.
Return to Summary Table.
When this register is written, the flash memory controller initiates the appropriate access cycle for the
location specified by the Flash Memory Address (FMA) register. If the access is a write access, the data in
the Flash Write Buffer (FWB) registers is written. This register must be the final register written, as it
initiates the memory operation.
Figure 21-7. FMC2 Register
31 30 29 28 27 26 25 24
WRKEY
W-0h
23 22 21 20 19 18 17 16
WRKEY
W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WRBUF
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-8. FMC2 Register Field Descriptions
Bit Field Type Reset Description
31-16 WRKEY W 0h
Flash Memory Write Key
This field contains a write key, which is used to minimize the
incidence of accidental flash memory writes. The value 0xA442 is
used as a key to initiate the appropriate access cycle for the location
specified by the address in the FMA register. Writes to the FMC2
register without this WRKEY value are ignored. A read of this field
returns the value 0.
15-1 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
0 WRBUF R/W 0h
Buffered Flash Memory Write
This bit is used to start a buffered write to flash memory. When read,
1 indicates that the previous buffered flash memory write access is
not complete.
0h = A write of 0 has no effect on the state of this bit. When read, 0
indicates that the previous buffered flash memory write access is
complete.
1h = Set this bit to write the data stored in the FWBn registers to the
location specified by the contents of the FMA register.