Texas Instruments CC3235 SimpleLink Series - I2 CSWRST Register; I2 CSWRST Register Field Descriptions

www.ti.com PRCM Registers
571
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Power, Reset, and Clock Management
15.6.41 I2CSWRST Register (offset = DCh) [reset = 0h]
I2CSWRST is shown in Figure 15-44 and described in Table 15-44.
Figure 15-44. I2CSWRST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENSTS SWRST
R-0h R-0h R/W-0h
Table 15-44. I2CSWRST Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 ENSTS R 0h
I2C_ENABLED_STATUS
0h = I
2
C clocks and resets are disabled
1h = I
2
C clocks and resets are enabled
0 SWRST R/W 0h
I2C_SOFT_RESET
0h = Deassert the soft reset for Shared-I2C
1h = Assert the soft reset for Shared-I2C