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SWRU543–January 2019
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-M4 Peripherals
3.3.1.22 HFAULTSTAT Register (Offset = D2Ch) [reset = 0h]
HFAULTSTAT is shown in Figure 3-22 and described in Table 3-25.
Return to Summary Table.
The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are
cleared by writing a 1 to them.
NOTE: This register can only be accessed from privileged mode.
Figure 3-22. HFAULTSTAT Register
31 30 29 28 27 26 25 24
DBG FORCED RESERVED
R/W1C-0h R/W1C-0h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED VECT RESERVED
R-0h R/W1C-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-25. HFAULTSTAT Register Field Descriptions
Bit Field Type Reset Description
31 DBG R/W1C 0h
Debug Event
This bit is reserved for debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.
30 FORCED R/W1C 0h
Forced Hard Fault
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault. This bit is cleared by
writing a 1 to it.
0h = No forced hard fault has occurred.
1h = A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because of
priority or because it is disabled.
29-2 RESERVED R 0h
1 VECT R/W1C 0h
Vector Table Read Fault
This error is always handled by the hard fault handler. When this bit
is set, the PC value stacked for the exception return points to the
instruction that was preempted by the exception. This bit is cleared
by writing a 1 to it.
0h = No bus fault has occurred on a vector table read.
1h = A bus fault occurred on a vector table read.
0 RESERVED R 0h
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