Texas Instruments CC3235 SimpleLink Series - GPIO Registers

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SWRU543–January 2019
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General-Purpose Input/Outputs (GPIOs)
5.5 GPIO Registers
Table 5-3 lists the GPIO memory-mapped registers. Each GPIO port can be accessed through the
advanced peripheral bus (APB). The offset listed is a hexadecimal increment to the register address,
relative to the base address of that GPIO port:
• GPIO Port A0: 0x4000.4000
• GPIO Port A1: 0x4000.5000
• GPIO Port A2: 0x4000.6000
• GPIO Port A3: 0x4000.7000
• GPIO Port A4: 0x4002 4000
Each GPIO module clock must be enabled before the registers can be programmed. There must be a
delay of three system clocks after the GPIO module clock is enabled before any GPIO module registers
are accessed.
(1)
This register is outside of the GPIO module. The physical address is 0x400F 70C8.
Table 5-3. GPIO Registers
Offset Acronym Register Name Section
0h GPIODATA GPIO Data Section 5.5.1
400h GPIODIR GPIO Direction Section 5.5.2
404h GPIOIS GPIO Interrupt Sense Section 5.5.3
408h GPIOIBE GPIO Interrupt Both Edges Section 5.5.4
40Ch GPIOIEV GPIO Interrupt Event Section 5.5.5
410h GPIOIM GPIO Interrupt Mask Section 5.5.6
414h GPIORIS GPIO Raw Interrupt Status Section 5.5.7
418h GPIOMIS GPIO Masked Interrupt Status Section 5.5.8
41Ch GPIOICR GPIO Interrupt Clear Section 5.5.9
- GPIO_TRIG_EN
(1)
GPIO Trigger Enable Section 5.5.10