Camera Registers
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SWRU543–January 2019
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Parallel Camera Interface Module
14.6.2 CC_SYSSTATUS Register (Offset = 14h) [reset = X]
Register mask: FFFFFFFEh
CC_SYSSTATUS is shown in Figure 14-10 and described in Table 14-5.
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This register provides status information about the module, excluding the interrupt status information (CCP
and parallel mode)
Figure 14-10. CC_SYSSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ResetDone
R-0h R-X
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-5. CC_SYSSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 ResetDone R X
Internal Reset Monitoring
0h = Internal module reset is ongoing.
1h = Reset completed