Texas Instruments CC3235 SimpleLink Series - SPI_SYSCONFIG Register

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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.6.1 SPI_SYSCONFIG Register (offset = 10h) [reset = 0h]
SPI_SYSCONFIG is shown in Figure 8-20 and described in Table 8-7.
Clock management configuration.
Figure 8-20. SPI_SYSCONFIG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SOFTRESET
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-7. SPI_SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 SOFTRESET R/W 0h Software reset. (Optional)
0h (W) = No action
0h (R) = Reset done, no pending action
1h (W) = Initiate software reset
1h (R) = Reset (software or other) ongoing